Static Timing Analysis

Project : lcd_2x16
Build Time : 08/29/21 06:10:44
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 67.000 MHz 67.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 67.000 MHz 67.000 MHz N/A
CyPLL_OUT CyPLL_OUT 67.000 MHz 67.000 MHz N/A